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Implementation and Performance Comparison of Digital Filter in FPGA


Scalable and Secure Big Data I

3D Reconstruction in Canonical
Abstract


This paper describes the design of different variants of Finite Impulse Response (FIR) filters, their implementation in Field Programmable Gate Array (FPGA) and the performance comparison using a hardware platform. The coefficients of filters are expressed in signed integer term to design a synthesizable optimal finite word length digital filter. This paper is focused on the design structure, resource usage and occupied silicon space, needed for implementation in FPGA. Multiple types of digital filters are tested using MATLAB out of which two filter design techniques, Gaussian window filter and Least square linear phase FIR filter are considered for illustration. The designed filters are synthesized and implemented using the HDL code generated by ‚??hdl coder‚?? tool of MATLAB. FIR filter is also realized using pre-implemented Soft-IP Core provided by the FPGA manufacturer. Finally the filters are implemented on a hardware platform and compared to study their real time performance and the resource utilization of FPGA.

KeyWords
Digital filter, FPGA, Gauss window filter, Least square filter, performance comparison



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