A Low Cost High Performance VLSI Architecture for Image Scaling in Multimedia Applications
Image scaling refers to the resizing of an image and is done quite often during Digital Image Processing. In this paper, an efficient image scaling algorithm and its architecture is developed which produce good quality resized image with lesser area and high performance. It uses a linear space-variant edge detector for edge enhancement and a spatial sharp filter for reducing the blurring effects produced by the bilinear interpolation. A simplified bilinear interpolation is used which is hardware efficient. The proposed and the existing algorithms are implemented in Matlab. Quality of the image is assessed by the Peak Signal to Noise Ratio (PSNR) and Structural Similarity (SSIM) parameters. Hardware implementation is done using Verilog hardware description language and synthesized in Cadence Genus tool using GPDK 90-nm CMOS process.
Image scaling, spatial sharp filter, edge detection, simplified bilinear interpolation