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xUAVs: Towards Efficient Approximate Computing for UAVsLow Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization


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Abstract


High Denition (HD) image processing and real-time analytics over live video feeds have always been the key requirements for Intelligence, Surveillance and Reconnaissance (ISR) applications. With the evolution of optics and image enhancement techniques, computational loads of HD ISR systems are also rising exponentially. On the contrary, the slow-down of Moore's Law has recently posed challenging bounds over the level of achievable miniaturization for emerging processing and storage units. Field Programmable Gate Arrays (FPGAs) offer a popular choice of implementing ISR algorithms over resource-constrained platforms, such as Unmanned Aerial Vehicles (UAVs), due to favorable features of recongurability and rapid prototyping. A promising solution to bridge the gap between resource-constrained host platforms and computation-intensive FPGA applications is the paradigm of Approximate Computing. It compromises on the accuracy of processed results to offer signicant performance gains for error-tolerant applications, such as video and image processing. In this paper, we present a novel approximate adder design methodology, for FPGA-based systems with improved SWaP performance, besides preserving the accuracy requirements within acceptable thresholds. The design methodology proposed in this paper focuses on the FPGA-specic Look-Up Table (LUT) architecture to introduce approximations while splitting the carry chain into LUT-based sub-adders, with exible overlap to tune the adder's accuracy and achieve the overall latency of a single LUT. The paper presents several variants of the proposed design and offers application-oriented exibility to adjust for optimal SWaP vs accuracy trade-off. We have further devised a comprehensive assessment approach to verify functional viability of the proposed atomic arithmetic blocks at system level, through their implementation into dense computational imaging applications, such as 2-dimensional Discrete Cosine Transform (DCT), airborne self-localization and moving object tracking algorithms, in comparison with other state-of-the-art adders. Our most accurate design performs at least 9.9% better in power consumption when compared with existing approximate adders, which proves that the proposed methodology holds promising potential to improve SWaP-index for computation-intensive UAV applications.

KeyWords
Aerial ISR applications, approximate adders, approximate computing, FPGA, moving object tracking, self-localization



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